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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4R64CPE6C
Direct RambusTM DRAM RIMMTM Module 64M-BYTE (32M-WORD x 16-BIT)
Description
The Direct Rambus RIMM module is a general-purpose high-performance memory module subsystem suitable for use in a broad range of applications including computer memory, personal computers, workstations, and other applications where high bandwidth and low latency are required. MC-4R64CPE6C modules consists of four 128M Direct Rambus DRAM (Direct RDRAMTM) devices (PD488448). These are extremely high-speed CMOS DRAMs organized as 8M words by 16 bits. The use of Rambus Signaling Level (RSL) technology permits 600MHz, 711MHz or 800MHz transfer rates while using conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10 ns per sixteen bytes). The architecture of the Direct RDRAM enables the highest sustained bandwidth for multiple, simultaneous, randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95 % bus efficiency. The Direct RDRAM's 32 banks support up to four simultaneous transactions per device.
Features
* 184 edge connector pads with 1mm pad spacing * 64 MB Direct RDRAM storage * Each RDRAM(R) has 32 banks, for 128 banks total on module * Gold plated contacts * RDRAMs use Chip Scale Package (CSP) * Serial Presence Detect support * Operates from a 2.5 V supply * Low power and powerdown self refresh modes * Separate Row and Column buses for higher efficiency * Over Drive Factor (ODF) support
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. M14805EJ2V0DS00 (2nd edition) Date Published August 2000 NS CP (K) Printed in Japan
The mark 5 shows major revised points.
(c)
2000
MC-4R64CPE6C
Order information
Part number Organization I/O Freq. MHz MC-4R64CPE6C - 845 MC-4R64CPE6C - 745 MC-4R64CPE6C - 653 32M x 16 800 711 600 RAS access time ns 45 45 53 184 edge connector pads RIMM with heat spreader Edge connector : Gold plated 4 pieces of Package Mounted devices
PD488448FF
FBGA (BGA(R)) package
2
Preliminary Data Sheet M14805EJ2V0DS00
MC-4R64CPE6C
Module Pad Configuration
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46
GND LDQA7 GND LDQA5 GND LDQA3 GND LDQA1 GND LCFM GND LCFMN GND NC GND LROW2 GND LROW0 GND LCOL3 GND LCOL1 GND LDQB0 GND LDQB2 GND LDQB4 GND LDQB6 GND LDQB8 GND LCMD VCMOS SIN VCMOS NC GND NC VDD VDD NC NC NC NC
GND LDQA8 GND LDQA6 GND LDQA4 GND LDQA2 GND LDQA0 GND LCTMN GND LCTM GND NC GND LROW1 GND LCOL4 GND LCOL2 GND LCOL0 GND LDQB1 GND LDQB3 GND LDQB5 GND LDQB7 GND LSCK VCMOS SOUT VCMOS NC GND NC VDD VDD NC NC NC NC
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46
LCFM, LCFMN,
Side B Side A
RCFM, RCFMN : Clock from master LCTM, LCTMN, RCTM, RCTMN : Clock to master LCMD, RCMD : Serial Command Pad
B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92
NC NC NC NC VREF GND SA0 VDD SA1 SVDD SA2 VDD RCMD GND RDQB8 GND RDQB6 GND RDQB4 GND RDQB2 GND RDQB0 GND RCOL1 GND RCOL3 GND RROW0 GND RROW2 GND NC GND RCFMN GND RCFM GND RDQA1 GND RDQA3 GND RDQA5 GND RDQA7 GND
NC NC NC NC VREF GND SCL VDD SDA SVDD SWP VDD RSCK GND RDQB7 GND RDQB5 GND RDQB3 GND RDQB1 GND RCOL0 GND RCOL2 GND RCOL4 GND RROW1 GND NC GND RCTM GND RCTMN GND RDQA0 GND RDQA2 GND RDQA4 GND RDQA6 GND RDQA8 GND
A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92
LROW2 - LROW0, RROW2 - RROW0 : Row bus LCOL4 - LCOL0, RCOL4 - RCOL0 LDQA8 - LDQA0, RDQA8 - RDQA0 LDQB8 - LDQB0, RDQB8 - RDQB0 SA0 - SA2 SCL, SDA SIN, SOUT SVDD SWP VCMOS VDD VREF GND NC : Data bus B LSCK, RSCK : Clock input : Serial Presence Detect Address : Serial Presence Detect Clock : Serial I/O : SPD Voltage : Serial Presence Detect Write Protect : Supply voltage for serial pads : Supply voltage : Logic threshold : Ground reference : These pads are not connected : Data bus A : Column bus
Preliminary Data Sheet M14805EJ2V0DS00
3
MC-4R64CPE6C
Module Pad Names
Pad A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 Signal Name GND LDQA8 GND LDQA6 GND LDQA4 GND LDQA2 GND LDQA0 GND LCTMN GND LCTM GND NC GND LROW1 GND LCOL4 GND LCOL2 GND LCOL0 GND LDQB1 GND LDQB3 GND LDQB5 GND LDQB7 GND LSCK VCMOS SOUT VCMOS NC GND NC VDD VDD NC NC NC NC Pad B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 Signal Name GND LDQA7 GND LDQA5 GND LDQA3 GND LDQA1 GND LCFM GND LCFMN GND NC GND LROW2 GND LROW0 GND LCOL3 GND LCOL1 GND LDQB0 GND LDQB2 GND LDQB4 GND LDQB6 GND LDQB8 GND LCMD VCMOS SIN VCMOS NC GND NC VDD VDD NC NC NC NC Pad A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 Signal Name NC NC NC NC VREF GND SCL VDD SDA SVDD SWP VDD RSCK GND RDQB7 GND RDQB5 GND RDQB3 GND RDQB1 GND RCOL0 GND RCOL2 GND RCOL4 GND RROW1 GND NC GND RCTM GND RCTMN GND RDQA0 GND RDQA2 GND RDQA4 GND RDQA6 GND RDQA8 GND Pad B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92 Signal Name NC NC NC NC VREF GND SA0 VDD SA1 SVDD SA2 VDD RCMD GND RDQB8 GND RDQB6 GND RDQB4 GND RDQB2 GND RDQB0 GND RCOL1 GND RCOL3 GND RROW0 GND RROW2 GND NC GND RCFMN GND RCFM GND RDQA1 GND RDQA3 GND RDQA5 GND RDQA7 GND
4
Preliminary Data Sheet M14805EJ2V0DS00
MC-4R64CPE6C
Module Connector Pad Description
Signal GND LCFM I/O - I Type - RSL Description Ground reference for RDRAM core and interface. 72 PCB connector pads. Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. LCFMN I RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. LCMD I VCMOS Serial Command used to read from and write to the control registers. Also used for power management. LCOL4..LCOL0 I RSL Column bus. 5-bit bus containing control and address information for column accesses. LCTM I RSL Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. LCTMN I RSL Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. LDQA8..LDQA0 I/O RSL Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. LDQA8 is non-functional on modules with x16 RDRAM devices. LDQB8..LDQB0 I/O RSL Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. LDQB8 is non-functional on modules with x16 RDRAM devices. LROW2..LROW0 LSCK I I RSL VCMOS Row bus. 3-bit bus containing control and address information for row accesses. Serial clock input. Clock source used to read from and write to the RDRAM control registers. NC - - These pads are not connected. These 24 connector pads are reserved for future use. RCFM RCFMN RCMD RCOL4..RCOL0 RCTM RCTMN RDQA8..RDQA0 I I I I I I I/O RSL RSL VCMOS RSL RSL RSL RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. Serial Command Input used to read from and write to the control registers. Also used for power management. Column bus. 5-bit bus containing control and address information for column accesses. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. RDQA8 is non-functional on modules with x16 RDRAM devices. RDQB8..RDQB0 I/O RSL Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. RDQB8 is non-functional on modules with x16 RDRAM devices. RROW2..RROW0 I RSL Row bus. 3-bit bus containing control and address information for row accesses.
(1/2)
Preliminary Data Sheet M14805EJ2V0DS00
5
MC-4R64CPE6C
(2/2)
Signal RSCK SA0 SA1 SA2 SCL SDA SIN SOUT SVDD SWP VCMOS VDD VREF I/O I I I I I I/O I/O I/O -- I -- -- -- Type VCMOS SVDD SVDD SVDD SVDD SVDD VCMOS VCMOS -- SVDD -- -- -- Description Serial clock input. Clock source used to read from and write to the RDRAM control registers. Serial Presence Detect Address 0. Serial Presence Detect Address 1. Serial Presence Detect Address 2. Serial Presence Detect Clock. Serial Presence Detect Data (Open Collector I/O). Serial I/O for reading from and writing to the control registers. Attaches to SIO0 of the first RDRAM on the module. Serial I/O for reading from and writing to the control registers. Attaches to SIO1 of the last RDRAM on the module. SPD Voltage. Used for signals SCL, SDA, SWP, SA0, SA1 and SA2. Serial Presence Detect Write Protect (active high). When low, the SPD can be written as well as read. CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT. Supply voltage for the RDRAM core and interface logic. Logic threshold reference voltage for RSL signals.
6
Preliminary Data Sheet M14805EJ2V0DS00
MC-4R64CPE6C
Remarks 1. Rambus Channel signals form a loop through the RIMM module, with the exception of the SIO chain.
VDD VCMOS
SDA
SIN LSCK LCMD VREF
SCL
Block Diagram
WP
SOUT RSCK RCMD
SCL
SWP
47 k
SA0 SA1 SA2
SVDD
VCC
U0
A0
A1
A2
LDQA 8 LDQA 7 LDQA 6 LDQA 5 LDQA 4 LDQA 3 LDQA 2 LDQA 1 LDQA 0 LCFM LCFMN LCTM LCTMN LROW 2 LROW 1 LROW 0 LCOL 4 LCOL 3 LCOL 2 LCOL 1 LCOL 0 LDQB 0 LDQB 1 LDQB 2 LDQB 3 LDQB 4 LDQB 5 LDQB 6 LDQB 7 LDQB 8
DQA 8 DQA 7 DQA 6 DQA 5 DQA 4 DQA 3 DQA 2 DQA 1 DQA 0 CFM CFMN CTM CTMN ROW 2 ROW 1 ROW 0 COL 4 COL 3 COL 2 COL 1 COL 0 DQB 0 DQB 1 DQB 2 DQB 3 DQB 4 DQB 5 DQB 6 DQB 7 DQB 8 DQA 8 DQA 7 DQA 6 DQA 5 DQA 4 DQA 3 DQA 2 DQA 1 DQA 0 CFM CFMN CTM CTMN ROW 2 ROW 1 ROW 0 COL 4 COL 3 COL 2 COL 1 COL 0 DQB 0 DQB 1 DQB 2 DQB 3 DQB 4 DQB 5 DQB 6 DQB 7 DQB 8 DQA 8 DQA 7 DQA 6 DQA 5 DQA 4 DQA 3 DQA 2 DQA 1 DQA 0 CFM CFMN CTM CTMN ROW 2 ROW 1 ROW 0 COL 4 COL 3 COL 2 COL 1 COL 0 DQB 0 DQB 1 DQB 2 DQB 3 DQB 4 DQB 5 DQB 6 DQB 7 DQB 8
DQA 8 DQA 7 DQA 6 DQA 5 DQA 4 DQA 3 DQA 2 DQA 1 DQA 0 CFM CFMN CTM CTMN ROW 2 ROW 1 ROW 0 COL 4 COL 3 COL 2 COL 1 COL 0 DQB 0 DQB 1 DQB 2 DQB 3 DQB 4 DQB 5 DQB 6 DQB 7 DQB 8
RDQA 8 RDQA 7 RDQA 6 RDQA 5 RDQA 4 RDQA 3 RDQA 2 RDQA 1 RDQA 0 RCFM RCFMN RCTM RCTMN RROW 2 RROW 1 RROW 0 RCOL 4 RCOL 3 RCOL 2 RCOL 1 RCOL 0 RDQB 0 RDQB 1 RDQB 2 RDQB 3 RDQB 4 RDQB 5 RDQB 6 RDQB 7 RDQB 8
2. See Serial Presence Detection Specification for information on the SPD device and its contents.
U2 U3 U1 U4 SIO 0 SIO 1 SIO 0 SIO 0 SIO 1 SIO 0 SIO 1 SIO 1 CMD CMD CMD CMD VREF VREF VREF SCK SCK VREF SCK SCK
2 per RDRAM 0.1 F
1 per 2 RDRAMs 0.1 F
VREF
1 per 2 RDRAMs Plus one Near Connector 0.1 F
SERIAL PD
SDA
Preliminary Data Sheet M14805EJ2V0DS00
SVDD
0.1 F
VCMOS
VDD
7
MC-4R64CPE6C
Electrical Specification
Absolute Maximum Ratings
Symbol VI,ABS VDD,ABS TSTORE Parameter Voltage applied to any RSL or CMOS signal pad with respect to GND Voltage on VDD with respect to GND Storage temperature MIN. -0.3 -0.5 -50 MAX. VDD + 0.3 VDD + 1.0 +100 Unit V V C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
DC Recommended Electrical Conditions
Symbol VDD VCMOS Parameter and conditions Supply voltage CMOS I/O power supply at pad 2.5V controllers 1.8V controllers VREF VIL VIH VIL,CMOS VIH,CMOS VOL,CMOS VOH,CMOS IREF ISCK,CMD ISIN,SOUT Reference voltage RSL input low voltage RSL input high voltage CMOS input low voltage CMOS input high voltage CMOS output low voltage, IOL,CMOS = 1 mA CMOS output high voltage, IOH,CMOS = -0.25 mA VREF current, VREF,MAX CMOS input leakage current, (0 VCMOS VDD) CMOS input leakage current, (0 VCMOS VDD) MIN. 2.50 - 0.13 2.5 - 0.13 1.8 - 0.1 1.4 - 0.2 VREF - 0.5 VREF + 0.2 -0.3 0.5VCMOS+0.25 MAX. 2.50 + 0.13 2.5 + 0.25 1.8 + 0.2 1.4 + 0.2 VREF - 0.2 VREF + 0.5 0.5VCMOS - 0.25 VCMOS + 0.3 0.3 V V V V V V V Unit V V
--
VCMOS - 0.3 -40.0 -40.0 -10.0
--
+40.0 +40.0 +10.0
A A A
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Preliminary Data Sheet M14805EJ2V0DS00
MC-4R64CPE6C
AC Electrical Specifications
Symbol Parameter and Conditions Module Impedance Average clock delay from finger to finger of all RSL clock nets (CTM, CTMN,CFM, and CFMN) -845 -745 -653 TPD TPD-CMOS Propagation delay variation of RSL signals with respect to TPD
Note1,2
MIN. 25.2
TYP. 28
MAX. 30.8 1.25 1.25 1.25
Unit ns
*
Z TPD
-21 -100
+21 +100
ps ps
Propagation delay variation of SCK and CMD signals with respect to an average clock delay
Note1
V/VIN
Attenuation Limit
-845 -745 -653
12 12 8 2 2 2 1.5 1.5 1.5 0.6 0.6 0.6
%
VXF/VIN
Forward crosstalk coefficient (300ps input rise time 20% - 80%)
-845 -745 -653
%
VXB/VIN
Backward crosstalk coefficient (300ps input rise time 20% - 80%)
-845 -745 -653
%
RDC
DC Resistance Limit
-845 -745 -653
Notes 1. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM, CTMN, CFM, and CFMN). 2. If the RIMM module meets the following specification, then it is compliant to the specification. If the RIMM module does not meet these specifications, then the specification can be adjusted by the "Adjusted TPD Specification" table. Adjusted TPD Specification
Symbol Parameter and conditions Adjusted MIN./MAX. Absolute MIN. TPD Propagation delay variation of RSL signals with respect to TPD +/- [17+(18*N*Z0)] Note -30 MAX. +30 ps Unit
Note N = Number of RDRAM devices installed on the RIMM module. Z0 = delta Z0% = (MAX. Z0 - MIN. Z0) / (MIN. Z0) (MAX. Z0 and MIN. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers on the module.)
Preliminary Data Sheet M14805EJ2V0DS00
9
MC-4R64CPE6C
RIMM Module Current Profile
IDD IDD1 RIMM module power conditions Note1 One RDRAM in Read
Note2
MAX. -845 -745 -653 702.6 637.6 552.6 1,020 940 825 1,230 1,120 975 662.6 607.6 527.6 980 910 800 1,190 1,090 950
Unit mA
, balance in NAP mode
IDD2
One RDRAM in Read Note2, balance in Standby mode
-845 -745 -653
mA
IDD3
One RDRAM in Read
Note2
, balance in Active mode
-845 -745 -653
mA
IDD4
One RDRAM in Write, balance in NAP mode
-845 -745 -653
mA
IDD5
One RDRAM in Write, balance in Standby mode
-845 -745 -653
mA
IDD6
One RDRAM in Write, balance in Active mode
-845 -745 -653
mA
Notes 1. Actual power will depend on individual RDRAM component specifications, memory controller and usage patterns. Power does not include Refresh Current. 2. I/O current is a function of the % of 1's, to add I/O power for 50 % 1's for a x16 need to add 257 mA for the following : VDD = 2.5 V, VTERM = 1.8 V, VREF = 1.4 V and VDIL = VREF - 0.5 V.
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Preliminary Data Sheet M14805EJ2V0DS00
MC-4R64CPE6C
Timing Parameters The following timing parameters are from the RDRAMs pins, not the RIMM. Please refer to the RDRAM data sheet (PD488448) for detailed timing diagrams.
Parameter tRC tRAS tRP Row Cycle time of RDRAM banks - the interval between ROWA packets with ACT commands to the same bank. RAS-asserted time of RDRAM bank - the interval between ROWA packet with ACT command and next ROWR packet with PRER Note 1 command to the same bank. Row Precharge time of RDRAM banks - the interval between ROWR packet with PRER Note 1 command and next ROWA packet with ACT command to the same bank. tPP Precharge-to-precharge time of RDRAM device - the interval between successive ROWR packets with PRER Note 1 commands to any banks of the same device. tRR RAS-to-RAS time of RDRAM device - the interval between successive ROWA packets with ACT commands to any banks of the same device. RAS-to-CAS Delay - the interval from ROWA packet with ACT command to COLC packet with RD or WR command. Note - the RAS-to-CAS delay seen by the RDRAM core (tRCD-C) is equal to tRCD-C = 1 + tRCD because of differences in the row and column paths through the RDRAM interface. CAS Access delay - the interval from RD command to Q read data. The equation for tCAC is given in the TPARM register. CAS Write Delay - interval from WR command to D write data. CAS-to-CAS time of RDRAM bank - the interval between successive COLC commands. Length of ROWA, ROWR, COLC, COLM or COLX packet. Interval from COLC packet with WR command to COLC packet which causes retire, and to COLM packet with bytemask. The interval (offset) from COLC packet with RDA command, or from COLC packet with retire command (after WRA automatic precharge), or from COLC packet with PREC command, or from COLX packet with PREX command to the equivalent ROWR packet with PRER. The equation for tOFFP is given in the TPARM register. Interval from last COLC packet with RD command to ROWR packet with PRER. Interval from last COLC packet with automatic retire command to ROWR packet with PRER. 8 8 8 -- tCYCLE 8 8 8 -- tCYCLE Description -845 28 20 8 MIN. -745 28 20 8 -653 28 20 8 --
Note 2
MAX.
Units
tCYCLE tCYCLE tCYCLE
64s --
tRCD
9
7
7
--
tCYCLE
tCAC tCWD tCC tPACKET tRTR
8 6 4 4 8
8 6 4 4 8
8 6 4 4 8
12 6 -- 4 --
tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE
tOFFP
4
4
4
4
tCYCLE
tRDP tRTP
4 4
4 4
4 4
-- --
tCYCLE tCYCLE
Notes 1. Or equivalent PREC or PREX command. 2. This is a constraint imposed by the core, and is therefore in units of ms rather than tCYCLE.
Preliminary Data Sheet M14805EJ2V0DS00
11
MC-4R64CPE6C
* Standard RIMM Module Marking
The RIMM modules available from NEC are marked per Figure 1 below. This marking assists users to specify and verify if the correct RIMM modules are installed in their systems. In the diagram, a label is shown attached to the RIMM module's heat spreader. Information contained on the label is specific to the RIMM module and provides RDRAM information without requiring removal of the RIMM module's heat spreader.
Figure 1. RIMM Module marking example
A
B
C
D
JAPAN 0020B9001
128MB/8d nonECC G100 S100
MC-4R128CEE6C-845 800-45
(c)1996 HCS, Inc. 800-748-0241 No. 6043B-ISO
G
E
H
I
F
J
Label Field A Vendor logo B Manufacturing Country Vendor logo area Country of origin
Description NEC
Marked Text - -
Units
JAPAN, USA, FRANCE
C Module Memory Capacity Number of 8-bit or 9-bit MBytes of RDRAM storage in 64MB, 96MB, 128MB, 192MB, RIMM module Number of RDRAMs Number of RDRAM devices contained in the RIMM module D ECC Support Indicates whether the RIMM module supports 8-bit (non ECC) or 9-bit (ECC) Bytes E Part No. F Memory Speed tRAC G Manufacturing Lot No. H Gerber Version I SPD Version J Caution Logo NEC RIMM Part No. Data transfer speed for RIMM module Row Access Time See table Order information 800, 711, 600 -45, -53 non ECC, ECC 256MB /4d, /6d, /8d, /12d, /16d
MBytes
RDRAM devices - - MHz ns - - - -
Manufactured Year code, Week code, In-house code YYWW PCB Gerber file revision used on RIMM Module SPD code version - G100 as Rev 1.00 S100 as Rev 1.00 -
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Preliminary Data Sheet M14805EJ2V0DS00
MC-4R64CPE6C
Package Drawings
184 EDGE CONNECTOR PADS RIMM (SOCKET TYPE) (1/2)
EEPROM
R P
A (AREA B)
128 M Direct RDRAM
M1 (AREA B)
V
S A L K H D B I E C A1 (AREA A) B J F
ON
M
Q
M2 (AREA A)
T
G
ITEM A A1 B B1 C
MILLIMETERS 133.35 TYP. 133.350.13 55.175 1.000.10 11.50 3.000.10 45.00 32.00 45.00 5.675 47.625 25.40 47.625 6.35 1.00 TYP. 31.750.13 11.97 19.78 29.21 17.78 4.000.10 R 2.00 3.000.10 2.44 1.270.10 2.43 MAX. 0.800.10 2.99 0.15 2.000.10
detail of A part W
detail of B part C1 R1.00
C1 D E F G H I J K L M M1 M2 N O P Q R S T V W X Y Z
R1.00
Y X
B1 Z
Preliminary Data Sheet M14805EJ2V0DS00
13
MC-4R64CPE6C
184 EDGE CONNECTOR PADS RIMM (SOCKET TYPE) (2/2)
Pad A1
, , ,,,,,,,,, ,,,,, ,,,,,,,,, ,,,,,,,,,
A E C C D
ITEM A B C D E F G H DESCRIPTION PCB length PCB height for 1.25" RIMM Module Center-center pad width from pad A1 to A46, A47 to A92, B1 to B46 or B47 to B92 Spacing from PCB left edge to connector key notch Spacing from contact pad PCB edge to side edge retainer notch PCB thickness Heat spreader thickness from PCB surface (one side) to heat spreader top surface RIMM thickness MIN. 133.22 31.62 44.95 1.17 TYP. 133.35 31.75 45.00 55.175 17.78 1.27 -
B F
Pad A92
G H
MAX. 133.48 31.88 45.05
UNIT mm mm mm mm mm mm mm mm
1.37 3.09 4.46
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Preliminary Data Sheet M14805EJ2V0DS00
MC-4R64CPE6C
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Preliminary Data Sheet M14805EJ2V0DS00
15
MC-4R64CPE6C
Rambus, RDRAM and the Rambus Logo are registered trademarks of Rambus Inc. DirectRambus, DirectRDRAM, RIMM, RModule and RSocket are trademarks of Rambus Inc.
BGA is a registered trademark of Tessera Inc.
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
* The information in this document is current as of August, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4

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